The GOA (Gate Driver on Array) technology, i.e. the array substrate row driving technology is to utilize the array manufacture process of the Thin Film Transistor (TFT) liquid crystal display to manufacture the gate driving circuit on the Thin Film Transistor array substrate for realizing the driving way of scanning the gates row by row. It possesses advantages of reducing the production cost and realizing the panel narrow frame design, and is utilized by many kinds of displays.
The GOA circuit has two basic functions: the first is to output the scan driving circuit for driving the gate lines in the panel to activate the TFTs in the display areas and to charge the pixels; the second is the shift register function. When the output of one scan driving signal is accomplished, the output of the next scan driving signal is performed with the control of the clock signal, and the transfer carries on in sequence.
With the development of Low Temperature Poly-Silicon (LTPS) semiconductor thin film transistor, the LTPS TFT liquid crystal display gradually becomes the focus that people pay lots of attentions. Because the silicon crystallization of the LTPS has better order than the amorphous silicon, and the LTPS semiconductor has ultra high carrier mobility, the liquid crystal display utilizing the LTPS TFT possesses advantages of high resolution, fast response speed, high brightness, high aperture ratio and et cetera. Correspondingly, the peripheral circuit around the LTPS TFT liquid crystal panel also becomes the focus that people pay lots of attentions.
FIG. 1 shows a CMOS GOA circuit according to prior art, comprising a plurality of GOA units which are cascade connected, wherein N is set to be a positive integer, and the nth GOA unit comprises: an input control module 100, a reset module 200, a latch module 300, a signal process module 400 and an output buffer module 500.
The input control module 100 receives a stage transfer signal Q(N−1) of the GOA unit circuit of the former stage, a first clock signal CK(1), a first inverted clock signal XCK(1), a constant high voltage level signal VGH and a constant low voltage level signal VGL, and is employed to input the signal P(N) which the voltage level is opposite to the stage transfer signal Q(N−1) of the GOA unit circuit of the former stage into the latch module 300. In the input control module 100, beside the fourth N type thin film transistor T4, the first clock signal CK(1) also controls an inverter constructed by the tenth P type thin film transistor T10 and the eleventh N type thin film transistor T11 to obtain the first inverted clock signal XCK(1).
The latch module 300 comprises an inverter F to invert the signal P(N) and obtains the stage transfer signal of the GOA unit circuit of the Nth stage, and the latch module 300 performs latch to the stage transfer signal Q(N). In the latch module 300, the first clock signal CK(1) needs to control the sixth P type thin film transistor T6.
The reset module 200 is employed to perform clear zero process to the stage transfer signal Q(N) of the GOA unit circuit of the Nth stage.
The signal process module 400 receives the latched stage transfer signal Q(N), the second clock signal CK(2), the constant high voltage level signal VGH and the constant low voltage level signal VGL, and is employed to implement NAND logic process to the second clock signal CK(2) and the stage transfer signal Q(N) to generate a scan driving signal G(N) of the GOA unit circuit of the Nth stage.
The output buffer module 500 is electrically couple to the signal process module 400 and employed to increase a driving ability of the scan driving signal Gate(N), and the working procedure of reducing the RC loading in the signal transmission process in the present CMOS GOA circuit is below:
As the high voltage level pulse of the stage transfer signal Q(N−1) of the former stage arrives, the first clock signal CK(1) is high voltage level, and then the first P type thin film transistor T1, the third N type thin film transistor T3 and the fourth N type thin film transistor T4 are activated, and the Q(N) node is charged to be high voltage level; as the function of the first clock signal CK(1) is finished, the first P type thin film transistor T1 and the fourth N type thin film transistor T4 are deactivated, and the sixth P type thin film transistor T6 and the ninth N type thin film transistor T9 are activated, and then, the stage transfer signal Q(N) is latched; as the high voltage level pulse of the second clock signal CK(2) arrives, the scan drive signal Gate(N) outputs high voltage level; as the function of the second clock signal CK(2) is finished, the scan drive signal Gate(N) is stabled at low voltage level.
As aforementioned, the present CMOS GOA circuit possesses excellent logic function but there is an inevitable problem, which is that the amount of the thin film transistors driven by the clock signal is more as the GOA circuit drives. For instance, as inputting the stage transfer signal, the clock signal needs to control four thin film transistors T4, T6, T10 and T11. Therefore, the clock signal needs to suffer a very large loading, which will lead to the RC delay and the power consumption increase of the clock signal.